Check the following if the project fails to build or generate a bitstream:
- Are you using the correct version of Vivado for this version of the repository?Check the version specified in the Requirements section of the README.md file. Note that this project is regularly maintained to the latest version of Vivado and you may have to refer to an earlier commit of this repo if you are using an older version of Vivado.
- Did you correctly follow the Build instructions in this readme file?All the projects in the repo are built, synthesised and implemented to a bitstream before being committed, so if you follow the instructions, there should not be any build issues.
- Did you copy/clone the repo into a short directory structure?Vivado doesn’t cope well with long directory structures, so copy/clone the repo into a short directory structure such as
C:\projects\. When working in long directory structures, you can get errors relating to missing files, particularly files that are normally generated by Vivado (FIFOs, etc).
Ports not working¶
Check the following if you are unable to get ports working in PetaLinux.
- Check the interface-to-port assignment for your designThe assignment of interfaces (eg. eth0, eth1, eth2, etc) to ports (eg. Ethernet FMC port 0, 1, 2 and 3) is specific to the design that you are using. The interface to port assignment is documented here.
- Each port must be assigned to a different subnetIf you assign interface eth0 to IP address 192.168.1.10, then you must use a different subnet for the IP address of eth1, eth2 and eth3. Multiple ports that are managed under Linux must be assigned to different subnets, or they will not work. An example address assignment would be eth0=192.168.1.10, eth1=192.168.2.10, eth2=192.168.3.10, eth3=192.168.4.10.
No dropped packets are to be expected with our example designs. If you are experiencing dropped packets of any kind, this can be an indication of one of the following issues:
Timing in the FPGA design is not optimal (check for timing errors in the Vivado design)
Timing of the RGMII interface is not optimal (can be due to the FPGA design or the PHY configuration)
We ensure that there are no timing errors or issues on all of our designs before making a release, so typically this problem occurs on custom designs where the timing issues have not yet been optimized. Please contact us for support if you are experiencing dropped packets.