Revision History

2025.2 Changes

  • Updated for Vivado / Vitis / PetaLinux 2025.2

  • Migrated standalone application to the Vitis Unified IDE Python flow (Vitis/py/build-vitis.py driven by args.json) — replaces the old XSCT batch flow

  • Switched to SDT-based BSP generation; XPAR macros are now *_BASEADDR rather than *_DEVICE_ID

  • Linux kernel 6.12, U-Boot 2025.01 from the AMD/Xilinx tree

  • AXI Ethernet interfaces are renamed by the kernel: enx<mac> on Zynq-7000, end<N> on Zynq UltraScale+

  • Per-board cma= reservation in the kernel command line is sized to the device’s DDR (256M / 512M / 1536M depending on target — see advanced)

  • Added a transient-sstate-fetch troubleshooting entry

  • Added the AMD Yocto / EDF build flow (in Yocto/) for the Zynq-7000 and Zynq UltraScale+ targets, alongside PetaLinux — see Yocto. The MACHINE is generated from the Vivado XSA via gen-machineconf parse-sdt, and the AXI Ethernet PHY wiring is supplied per target by port-config.dtsi overlay layers (ports-0123 / ports-01--). The PetaLinux flow for this repository will be retired after 2025.2 — Yocto / EDF is its successor

  • In the Yocto/EDF images the AXI Ethernet interfaces are end0–end3 on all targets (the EDF rootfs uses systemd predictable naming), unlike the PetaLinux enx<mac> names on Zynq-7000

  • Zynq-7000 Yocto kernel: enabled CONFIG_NFSD (the arm defconfig omits it), so the NFS server starts cleanly at boot as it does on Zynq UltraScale+

2025.2 update: Linux fixes, board Ethernet port, documentation

  • Yocto: AXI Ethernet ports failed to probe. The Yocto targets had no portcfg attribute in config/data.json, so the port-config overlay was never applied and the AXI Ethernet driver stopped with “phy-handle required”. All Yocto targets now name their overlay (ports-0123, ports-01-- for zcu102_hpc1).

  • Board Ethernet port on Zynq-7000 (Yocto and PetaLinux). GEM0 used to be disabled to avoid a U-Boot 2025.01 crash (the generated device tree enables GEM0 without describing its PHY). The PHY is now described instead (MDIO address 0 on ZedBoard and PicoZed, 7 on ZC702 and ZC706, rgmii-id), so U-Boot no longer crashes and the board’s own Ethernet port works under Linux, for example for SSH while the Ethernet FMC ports are under test.

  • Board Ethernet port on ZCU102 (Yocto). The link came up but passed no traffic because the device tree did not describe the TI DP83867 PHY and its RGMII delays. The PHY is now described in system-user.dtsi, and the port has a fixed MAC address.

  • Yocto kernel command line and hostname. The cma= reservation and the other board-specific kernel arguments set in local.conf.append never reached the kernel (the EDF boot flow ignores APPEND), and the hostname stayed amd-edf. The arguments are now appended to boot.scr from BSP_EXTRA_BOOTARGS, and the hostname is <board>-axieth-2025-2.

  • Yocto Zynq-7000 images also include bridge-utils, as the PetaLinux images do.

  • Yocto build on some Linux hosts. Yocto/scripts/hostfix.sh works around host tar versions that BitBake’s fake-root tool cannot handle.

  • Build runner. clean --keep-boot deletes the rebuildable intermediates of a target and keeps its deliverables; package now rewrites a boot-image zip when the artifacts are newer than the zip (it used to keep shipping an older image); the Yocto zip always contains BOOT.BIN.

  • Documentation. New block diagram and block-design diagram (generated by docs/source/images/gen_block_diagram.py and gen_bd_diagram.py), a description of how the design works, and how-to-test guides for the standalone echo server, PetaLinux and Yocto images (interface identification, DHCP / static IP, ethtool, phytool, iperf3 and the throughput to expect), plus a Linux troubleshooting section.

2024.1 Changes

  • Removed PetaLinux support for all pure FPGA designs

  • Improved documentation, centralized targed design info to JSON file

2022.1 Changes

  • Added Makefiles to improve the build experience for Linux users

  • Consolidated Vivado batch files (user is prompted to select target design)

  • Vitis build script now creates a separate workspace for each target design (improved user experience)

  • Converted documentation to markdown (from reStructuredText)

  • Removed the unnecessary postfix _axieth from all designs

  • Removed MicroZed FMC Carrier design (Avnet has discontinued the product).

  • Removed the PetaLinux projects for VC707, VC709 and VCU108 (AMD Xilinx releases no official BSP)