Revision History

2024.1 Changes

  • Removed PetaLinux support for all pure FPGA designs

  • Improved documentation, centralized targed design info to JSON file

2022.1 Changes

  • Added Makefiles to improve the build experience for Linux users

  • Consolidated Vivado batch files (user is prompted to select target design)

  • Vitis build script now creates a separate workspace for each target design (improved user experience)

  • Converted documentation to markdown (from reStructuredText)

  • Removed the unnecessary postfix _axieth from all designs

  • Removed MicroZed FMC Carrier design (Avnet has discontinued the product).

  • Removed the PetaLinux projects for VC707, VC709 and VCU108 (AMD Xilinx releases no official BSP)